A set of compact device models for a semiconductor technology typically includes a set of field-effect transistor (FET) device models, one or more passive device models (e.g., resistors, capacitors, inductors, etc.), and one or more interconnect models. Each model within the set of compact device models comprises nominal values of various process and/or model parameters as well as corresponding statistical variations. For example, typical model parameters for an interconnect model (i.e., wire) of a semiconductor technology includes wire length, wire width, wire thickness, etc., and the interconnect model returns wire resistance based on wire width and wire length as well as an index for a given interconnect level. By running a Monte Carlo simulation, which is typically time consuming, a distribution of wire resistance can also be obtained for a given wire width, and a minimum resistance bound and a maximum resistance bound for the given wire width can also be obtained. To reduce simulation time, often a set of corner models are developed. A corner model allows a single corner simulation run to obtain a minimum or maximum resistance value for a given wire width.